Title :
6.8 mW 2.5 Gb/s and 42.5 mW 5 Gb/s 1:8 CMOS demultiplexers
Author :
Cheng, Shanfeng ; Silva-Martinez, Jose
Author_Institution :
Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
Abstract :
This paper presents two low-power demultiplexers working at 2.5 Gbps and 5 Gbps input data rate respectively. The 2.5 Gbps demultiplexer consumes only 6.8 mW power dissipation. The 5 Gbps demultiplexer consumes 42.5 mW power dissipation. The two demultiplexers are implemented in TSMC 0.35 μm CMOS technology. They are built on the same chip sharing input and output ports. The power supply of the chip is 2.5 V. The demultiplexers are designed to be modules for optical communication receiver systems.
Keywords :
CMOS logic circuits; demultiplexing equipment; integrated circuit design; modules; optical receivers; 0.35 micron; 2.5 Gbit/s; 2.5 V; 42.5 mW; 5 Gbit/s; 6.8 mW; CMOS demultiplexers; CMOS technology; chip sharing input ports; chip sharing output ports; low-power demultiplexers; modules; optical communication receiver system; power dissipation; power supply; CMOS logic circuits; CMOS technology; Clocks; Costs; Optical design; Optical fiber communication; Optical receivers; Parallel architectures; Power dissipation; Power supplies;
Conference_Titel :
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN :
0-7803-8251-X
DOI :
10.1109/ISCAS.2004.1328977
