Construction of linearly transformed planar BDD by Walsh coefficients

Author

Karpovsky, Mark G. ; Stankovic, Radomir S. ; Astola, Jaakko T.

Author_Institution

Dept. of Electr. & Comput. Eng., Boston Univ., MA, USA

Volume

4

fYear

2004

fDate

23-26 May 2004

Abstract

In VLSI design, crossings of interconnections occupy space and cause delay. In particular, it is desirable to have planar networks for FPGA synthesis and sub-micron LSIs, since delays in the interconnections and crossings are comparable to the delays for logic circuits. Decision diagrams (DDs) provide a simple technology mapping, and planar DDs result in planar networks. In this paper, we present a deterministic method to construct planar Linearly Transformed Binary Decision Diagrams (BDDs) by Walsh transform spectral coefficients.

Keywords

VLSI; Walsh functions; binary decision diagrams; field programmable gate arrays; integrated circuit design; integrated circuit interconnections; large scale integration; FPGA synthesis; VLSI design; Walsh transform spectral coefficients; interconnection delays; interconnections crossings; linearly transformed planar BDD construction; logic circuit delays; planar linearly transformed binary decision diagrams; planar networks; submicron LSI; technology mapping; Binary decision diagrams; Circuit synthesis; Data structures; Delay; Field programmable gate arrays; Integrated circuit interconnections; Logic circuits; Network synthesis; Space technology; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1329054

Filename

1329054