Adaptive multiple resolution CMOS active pixel sensor

Author

Artyomov, Evgeny ; Yadid-Pecht, Orly

Author_Institution

VLSI Syst. Center, Ben-Gurion Univ., Beer-Sheva, Israel

Volume

4

fYear

2004

fDate

23-26 May 2004

Abstract

A smart image sensor with adaptive multiple resolution ability is presented. This sensor is based on the Quadtree Decomposition algorithm, which decomposes an image into square homogeneous regions. After the image is segmented, only the value of the block and its size are stored or transmitted. On chip implementation can solve the information bottleneck problem by reducing the amount of data for transmission. Good compression results can be achieved for scenes with predominant background. The algorithm is implemented on chip in a mixed signal, column parallel architecture in 0.35 μm 4M2P n-well TSMC CMOS technology available through MOSIS. Typical power dissipation for the test chip with 32×32 pixels is 70 mW at VDD=3.3 V.

Keywords

CMOS image sensors; data compression; image resolution; image segmentation; intelligent sensors; quadtrees; smart pixels; 0.35 micron; 3.3 V; 70 mW; CMOS active pixel sensor; CMOS technology; MOSIS; adaptive multiple resolution; column parallel architecture; data transmission; image decomposition; image segmentation; on chip implementation; power dissipation; quadtree decomposition algorithm; smart image sensor; square homogeneous region; test chip; CMOS image sensors; CMOS technology; Image coding; Image resolution; Image segmentation; Image sensors; Intelligent sensors; Layout; Parallel architectures; Power dissipation;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1329134

Filename

1329134