A Compact, Supply-Voltage Scalable 45–66 GHz Baseband-Combining CMOS Phased-Array Receiver

This paper presents a four-element phased-array receiver which achieves 38% fractional bandwidth around 55 GHz. Baseband phase-shifting is employed to eliminate wideband phase-shifters, power dividers, and quadrature splitters operating at millimeter-wave frequencies. Antenna weighting and combining are accomplished using a highly digital Cartesian phase-shifter and current summation, respectively. Transformer-coupling techniques are introduced in the LNA to simultaneously achieve wide bandwidth, reduced noise figure, gain boosting and neutralization. Cascode-free and folded topologies are used throughout to enable operation from a scalable supply voltage. To overcome challenges associated with wideband LO distribution, the LO network employs multiconductor transmission lines to distribute four-phase LO signals. The LO distribution network is absorbed into the LO buffers and terminated by distributed LC loads near the I/Q mixers in each phased-array element. The phased-array receiver is fabricated in a 45 nm SOI CMOS process and achieves 26.2 dB (20.2 dB) of element gain over 21 GHz (19 GHz) of 3 dB bandwidth with 5.5 dB/9.8 dB (7.7 dB/12 dB) minimum/maximum NF while dissipating 30 mW/element (14 mW/element) from a 1.1 V (0.6 V) supply voltage. The worst case -1 dB (input) compression is -28 dBm at 1.1 V. A worst case coupling of 26 dB (45 dB) is measured between adjacent (nonadjacent) elements. The IF bandwidth is 1.2 GHz, limited by the wirebond and PCB interface to the chip. The design occupies only 0.225 mm ² per element including LO buffer/distribution.