DocumentCode
418415
Title
CMOS APS imager employing 3.3 V 12 bit 6.3 MS/s pipelined ADC
Author
Hamami, Shy ; Fleshel, Leonid ; Yadid-Pecht, Orly
Author_Institution
VLSI Syst. Center, Ben-Gurion Univ., Beer-Sheva, Israel
Volume
4
fYear
2004
fDate
23-26 May 2004
Abstract
A novel 256×256 CMOS active pixel sensor (APS) system with 12 bit, 6.3 Msample/s (MS/s) CMOS pipelined analog to digital converter (ADC) integrated on chip is presented. The test chip has been implemented in 0.35 μm 2P4M process, operated by a 3.3 V supply and is expected to dissipate 55 mW. The total area of the prototype is 12 mm2, and the core area of ADC is 18% from the total area. System architecture and operation are discussed and simulation results are presented.
Keywords
CMOS image sensors; analogue-digital conversion; integrated circuit design; integrated circuit modelling; prototypes; 0.35 micron; 3.3 V; 55 mW; CMOS active pixel sensor; CMOS active pixel sensor imager; CMOS pipelined analog-digital converter; circuit simulation; pipelined ADC; power dissipation; prototype; system architecture; system operation; Analog-digital conversion; CMOS image sensors; Circuits; Decoding; Digital cameras; Parasitic capacitance; Photodiodes; Pixel; Sensor arrays; Sensor systems;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN
0-7803-8251-X
Type
conf
DOI
10.1109/ISCAS.2004.1329165
Filename
1329165
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