DocumentCode
418455
Title
A novel embedded memory architecture for real-time mesh-based motion estimation
Author
Sayed, Mohammed ; Badawy, Wael
Author_Institution
Dept. of Electr. & Comput. Eng., Calgary Univ., Alta., Canada
Volume
2
fYear
2004
fDate
23-26 May 2004
Abstract
This paper presents a novel embedded memory architecture for real-time mesh-based motion estimation. The proposed architecture stores the reference and the current frames and computes in memory the mesh nodes motion vectors. It uses regular triangular mesh structure. Parallel and pipelined implementations have been used to overcome the huge computational requirements of the motion estimation process. The proposed architecture has been designed, prototyped, and simulated for 0.18 μm CMOS TSMC technology. It can process 37 frames per second at 100 MHz clock frequency. It has a core area of 37.78 mm2, which includes 30.59 mm2 embedded SRAM to store two CIF frames.
Keywords
CMOS integrated circuits; embedded systems; memory architecture; mesh generation; motion estimation; parallel architectures; pipeline processing; CMOS technology; embedded SRAM; embedded memory architecture; embedded static random access memory; mesh nodes motion vector; motion estimation; parallel implementation; pipelined implementation; real time mesh based motion estimation; triangular mesh structure; CMOS technology; Clocks; Computational modeling; Computer architecture; Concurrent computing; Frequency; Memory architecture; Motion estimation; Random access memory; Virtual prototyping;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN
0-7803-8251-X
Type
conf
DOI
10.1109/ISCAS.2004.1329252
Filename
1329252
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