A distributed TS-MUX architecture for multi-chip extension beyond the HDTV level

This paper proposes a distributed stream multiplexing architecture for CODEC LSIs with multi-chip configuration, and demonstrates its scalability and usefulness. It consists of each media multiplexing unit with an external stream input and inter-chip communication interfaces. Parallel protocol processing, with an autonomous inter-chip control mechanism to mix and concatenate packets through daisy-chained transfer paths, provides a complete multi-chip output at the end of the chain. Dispensing with external stream handling devices contributes to both high throughput and downsizing. It is configurable for parallel encoding of super high-resolution video, multi-view/-angled HDTV vision and multiple HDTV channels. The architecture was implemented in a fabricated single-chip MPEG-2 422P@HL CODEC LSI and showed a good performance on an evaluation board system.