A low power current-mode pixel with on-chip FPN cancellation and digital shutter

In this paper, we describe an integrating current-mode CMOS pixel based on a novel reset/read-out strategy. In contrast to the conventional integrating mode pixel, here the reset and read-out phases of the imager are carried out simultaneously. In the new readout strategy, only two current sources are enabled at any given time, resulting in a power consumption that is independent of both read-out speed and imager array size, while still allowing for on read-out FPN cancellation. The addressing signals of the proposed read-out strategy are generated using conventional counters and an address decoders, which are also used to generate the addressing signals required for an electronic shutter, resulting in significant saving in silicon area. To demonstrate the benefits of the proposed approach and the pixel operation, a 32×32 imager has been integrated using AMIS CMOS 0.35 μm technology.