A fast Reed-Solomon Product-Code decoder without redundant computations

This paper presents a fast and low-power decoding scheme for Reed-Solomon Product-Code (RS-PC). To increase error correction capability of RS-PC, we need to repeat Reed-Solomon (RS) decoding several times for rows and columns. As the number of RS decodings increases, the execution time and the energy consumption also increase as well. In order to reduce unnecessary operations and memory accesses, we added two small memories to store data on whether the row or column is updated or not. In the next iteration, only the updated rows and columns are recalculated instead of the whole rows and columns. Based on the proposed scheme, we implemented a RS-PC decoder using UMC 0.25 μm standard and memory cells. The working frequency is 133 MHz at 2.5 V. Experimental results show that the execution time is reduced by 48% in case of four iterations, and by 66% in case of six iterations.