A fast Reed-Solomon Product-Code decoder without redundant computations

Author

Lee, Hyun-Yong ; Park, In-Cheol

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., KAIST, Daejeon, South Korea

Volume

2

fYear

2004

fDate

23-26 May 2004

Abstract

This paper presents a fast and low-power decoding scheme for Reed-Solomon Product-Code (RS-PC). To increase error correction capability of RS-PC, we need to repeat Reed-Solomon (RS) decoding several times for rows and columns. As the number of RS decodings increases, the execution time and the energy consumption also increase as well. In order to reduce unnecessary operations and memory accesses, we added two small memories to store data on whether the row or column is updated or not. In the next iteration, only the updated rows and columns are recalculated instead of the whole rows and columns. Based on the proposed scheme, we implemented a RS-PC decoder using UMC 0.25 μm standard and memory cells. The working frequency is 133 MHz at 2.5 V. Experimental results show that the execution time is reduced by 48% in case of four iterations, and by 66% in case of six iterations.

Keywords

Reed-Solomon codes; cellular arrays; decoding; error correction codes; iterative methods; power consumption; product codes; 0.25 micron; 133 MHz; 2.5 V; RS decoder; Reed-Solomon decoder; data storage; energy consumption; error correction; execution time reduction; iteration method; low power decoding; memory access; memory cells; product code decoder; redundant computations; standard cells; DVD; Energy consumption; Error correction; Error correction codes; Frequency; Iterative decoding; Memory; Reed-Solomon codes; Software performance; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1329288

Filename

1329288