DocumentCode :
418481
Title :
Novel bit manipulation unit for communication digital signal processors
Author :
Kim, Sung Dae ; Jeong, Sug Hyun ; Sunwoo, Myung Hoon ; Kim, Kyung Ho
Author_Institution :
Sch. of Electr. & Comput. Eng., Ajou Univ., Suwon, South Korea
Volume :
2
fYear :
2004
fDate :
23-26 May 2004
Abstract :
This paper proposes application-specific instructions and their bit manipulation unit (BMU), which efficiently support scrambling, convolutional encoding, puncturing, and interleaving. The proposed DSP employs the BMU supporting parallel shift and XOR (Exclusive-OR) operations and bit insertion/extraction operations on multiple data. The proposed architecture has been modeled by VHDL and synthesized using the SEC 0.18 μm standard cell library and the gate count of the BMU is only about 1700 gates. Performance comparisons show that the number of clock cycles can be reduced about 40%∼80% for scrambling, convolutional encoding and interleaving compared with existing DSPs.
Keywords :
application specific integrated circuits; cellular arrays; convolutional codes; digital communication; digital signal processing chips; encoding; hardware description languages; instruction sets; interleaved codes; logic arrays; DSP; VHDL; XOR operations; application specific instructions; bit insertion-extraction operations; bit manipulation unit; convolutional encoding; digital signal processor communication; exclusive OR operations; gate count; interleaved codes; parallel shift operations; scrambling units; standard cell library; Application specific integrated circuits; Convolution; Convolutional codes; Digital signal processing; Digital signal processing chips; Digital signal processors; Hardware; Interleaved codes; Shift registers; Wireless LAN;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN :
0-7803-8251-X
Type :
conf
DOI :
10.1109/ISCAS.2004.1329289
Filename :
1329289
Link To Document :
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