Pseudo-footless CMOS domino logic circuits for high-performance VLSI designs

Dynamic CMOS logic circuits, featuring a high-speed operation, are found pervasive in high-performance VLSI designs. This paper presents a new domino circuit that efficiently combines a pseudo-footless dynamic circuit technique with a robust self-timed delayed-evaluation clocking scheme to improve further the operation speed while without sacrificing the power consumption, even in the presence of process-voltage-temperature (PVT) variations. A 32-bit carry-look-ahead adder implemented with the new pseudo-footless domino circuit not only achieves 2 and 1.43 times speed improvement over the circuit implemented with the static CMOS and the conventional domino circuit, respectively, but also is the most power efficient dynamic design.