Title :
Modulo deflation in (2n+1, 2n, 2n-1) converters
Author :
Bi, Shaoqiang ; Wang, Wei ; Al-Khalili, Asim
Author_Institution :
Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
Abstract :
In this paper, a new modulo reduction theorem is introduced to decompose the base of the modulo operation. As one of possible applications, this new theorem can be used to further reduce the modulo size of the modified Chinese remainder theorem (CRT). Based on this new theorem, an improved modulo size reduced CRT algorithm for M={2n+1, 2n, 2n-1} is presented. For the most popular three-moduli set M, the design and FPGA implementation show that the proposed modulo part of the residue-to-binary(R/B) converter is almost twice faster and needs 50% less hardware and power than the modulo operation of the two converters previously published in the literature.
Keywords :
convertors; field programmable gate arrays; integrated circuit design; integrated circuit modelling; residue number systems; CRT algorithm; Chinese remainder theorem; FPGA; modulo deflation; modulo reduction theorem; residue-to-binary converters; Cathode ray tubes; Delay; Dynamic range; Field programmable gate arrays; Hardware; Neural networks; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN :
0-7803-8251-X
DOI :
10.1109/ISCAS.2004.1329300
