Switching activity in bit-serial constant-coefficient multipliers

Author

Johansson, Kenny ; Gustafsson, Oscar ; Wanhammar, Lars

Author_Institution

Dept. of Electr. Eng., Linkoping Univ., Sweden

Volume

2

fYear

2004

fDate

23-26 May 2004

Abstract

In this paper a method for computing the switching activity in bit-serial constant-coefficient multipliers is presented. The multipliers are described using a graph representation. It is shown that the average switching activity in all multipliers with up to four adders can be determined. Most of the switching activities can be obtained directly from the derived formulas and the remaining by using look-up tables. The switching activities are useful to estimate the power consumption, and makes it possible to choose the best power saving multiplier structure.

Keywords

adders; digital filters; digital signal processing chips; flip-flops; multiplying circuits; power consumption; shift registers; switching networks; table lookup; adders; bit-serial constant coefficient multipliers; look-up tables; power consumption; power saving multiplier structure; switching activity; Adders; CMOS digital integrated circuits; Capacitance; Clocks; Digital filters; Digital signal processing; Energy consumption; Flip-flops; Logic; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1329310

Filename

1329310