An experimental comparison of substrate noise generated by CMOS and by low-noise digital circuits

Two logic families, CSL (Current-Steering Logic) and CBL (Current-Balanced Logic), that have been proposed to reduce the substrate noise in mixed-signal integrated circuits, are compared with conventional CMOS by measurements on a test chip. Large CBL cells with wire bonding have a reduction of the substrate noise effect, with respect to CMOS, by a factor of 2.5, whereas CSL is noisier than CMOS. This agrees with the simulations. The moderate noise improvement shown in the simulations by CBL circuits with complementary outputs is not confirmed experimentally. The results here show that previous evaluations based on the amplitude of the supply current spikes are unsuitable to assess the real noise performance.