Low complexity digital PLL for instant acquisition CDR

Author

Allan, Gord ; Knight, John

Author_Institution

Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada

Volume

2

fYear

2004

fDate

23-26 May 2004

Abstract

A novel digital circuit is presented which, given one asynchronous training pulse, performs reliable clock and data recovery (CDR) on a bit-stream at rates up to 1.3 Ghz/Gbps. The circuit requires no analog components and is suitable for implementation on standard-cell ASICs or, at a reduced speed, on FPGAs. Unlike other digital PLLs, it does not oversample or use DSP arithmetic. It therefore consumes little area and power, but maintains range and stability. In one embodiment, in 0.18 μm, the circuit immediately locks to symbol rates from 1.3 Ghz - 420 Mhz, consumes 260 gates, insignificant static power, and less than 2 mW at 1 Ghz and full voltage.

Keywords

application specific integrated circuits; circuit complexity; digital phase locked loops; field programmable gate arrays; synchronisation; 0.18 micron; 1 GHz; 1.3 GHz to 420 MHz; DSP arithmetic; FPGA; analog components; asynchronous training pulse; bit stream; digital circuit; instant acquisition CDR; low complexity digital PLL; reliable clock and data recovery; standard cell ASIC; Clocks; Digital circuits; Filtering; Frequency; Integrated circuit interconnections; Low pass filters; Phase locked loops; Pulse circuits; Pulse measurements; Timing jitter;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1329333

Filename

1329333