Time borrowing and clock skew scheduling effects on multi-phase level-sensitive circuits

This paper addresses the effects of time borrowing and clock skew scheduling on level-sensitive synchronous circuits. Synchronization of level-sensitive circuits can be accomplished through single-phase or multi-phase clocking schemes. This paper expands previous single-phase clock signal analysis to include multiphase clock signal synchronization. The tradeoffs of synchronous circuit operation with different types of registers and synchronization schemes are analyzed. The presented timing analysis problem specifically targets clock period minimization. The modified big M method is used to linearize the formulation of the timing analysis problem and experiments are performed on the ISCAS´89 benchmark circuits. For single and multi-phase level-sensitive circuits, up to 63% and 62% improvements, respectively, over conventional zero-skew, flip-flop based circuits are achieved through the simultaneous application of both time borrowing and non-zero clock skew scheduling.