Efficient hardware implementation of a CRYPTO-MEMORY based on AES algorithm and SRAM architecture

This paper presents a CRYPTO-MEMORY based on Advanced Encryption Standard (AES) algorithm and SRAM architecture. The design of a dual-port SRAM has been modified by the addition of all logic operators required by the hardware implementation of AES. Moreover, a Finite State Machine has been included in order to allow a self-encryption in full autonomy. Consequently, compared to the classical scheme consisting of a crypto-block and a separated memory, this new design will lead to an important reduction of data transfers during the encryption process. So this will increase the security of sensitive data. This CRYPTO-MEMORY has a storage capacity of 32 k bits and is able to encrypt a 16*128-bit message using a 128-bit key. Its hardware implementation uses 386 k gates and encrypts a 128-bit message in 44 clock cycles.