Sampled analog architecture for DCT and DST

This paper describes an analog sampled data architecture, for computing either DCT or DST alternatively, using switched capacitor circuit and a resistor-string. The input samples are multiplied by all the DCT/DST coefficients concurrently using the resistor-string, and then switched properly with the help of a switching matrix, to different integrators for performing necessary addition/subtraction. The architecture may also be used for computing inverse transforms. Proposed architecture is simple, regular and can be used for online computations with moderate accuracy.