A fast and precise interconnect capacitive coupling noise model

Author

Lee, Young Jun ; Kim, Yong-Bin

Author_Institution

Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA

Volume

2

fYear

2004

fDate

23-26 May 2004

Abstract

This paper presents an accurate and fast method for calculating the time domain crosstalk noise for finite length on-chip distributed RC interconnect line. We begin with T. Sakurai´s crosstalk noise model and develop the new model by fitting the equation to HSPICE simulation data. The developed model was applied to long wires ranging from 1000 μm to 8000 μm, and the experiments in realistic environment demonstrate that the error between HSPICE simulation and the analysis using the proposed model is within ±10 percent for an 0.12 μm CMOS technology.

Keywords

CMOS integrated circuits; RC circuits; SPICE; integrated circuit interconnections; integrated circuit modelling; integrated circuit noise; system-on-chip; 0.12 micron; 1000 to 8000 micron; CMOS technology; HSPICE simulation data; Sakurai crosstalk noise model; finite length on chip distributed RC interconnect line; precise interconnect capacitive coupling noise model; time domain crosstalk noise; Analytical models; CMOS technology; Chromium; Circuit simulation; Crosstalk; Equations; Integrated circuit interconnections; Integrated circuit technology; Semiconductor device modeling; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1329411

Filename

1329411