DocumentCode
418547
Title
A high performance low power dynamic PLA with conditional evaluation scheme
Author
Oh, Kwang-Il ; Kim, Lee-Sup
Author_Institution
Dept. of EECS, KAIST, Daejeon, South Korea
Volume
2
fYear
2004
fDate
23-26 May 2004
Abstract
This paper proposes a high performance and low power dynamic CMOS PLA that minimizes active power consumption. The proposed PLA uses a conditional evaluation scheme to reduce short circuit power consumption during the evaluation phase. The proposed PLA reduces delay by 13.8%, dynamic power by 46%, and total power delay product (PDP) by 53.4% compared to the conventional clock-delayed PLA in a 0.25 μm CMOS process technology.
Keywords
CMOS logic circuits; low-power electronics; power consumption; programmable logic arrays; 0.25 micron; CMOS PLA; CMOS process; conditional evaluation scheme; low power dynamic PLA; phase evaluation; power delay product; short circuit power consumption; CMOS logic circuits; Capacitors; Clocks; Delay; Digital circuits; Energy consumption; Logic design; Performance evaluation; Programmable logic arrays; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN
0-7803-8251-X
Type
conf
DOI
10.1109/ISCAS.2004.1329413
Filename
1329413
Link To Document