Whirlpool hash function: architecture and VLSI implementation

New encryption algorithms have to operate in a variety of current and future applications demanding both high speed and high security. An architecture and VLSI implementation of the newest standard in the hash families, Whirlpool that achieves high-speed performance is presented. The architecture permits a wide variety of implementation tradeoffs. The design was coded using VHDL language and for the hardware implementation a FPGA device was used. While no other previous Whirlpool implementation exist, the comparison with previous hash families´ implementations such as MD5, SHA-1, SHA-2 etc are given. These comparisons prove that the Whirlpool implementation is much faster compared with these previous implementations.