A mixed-signal CMOS DTCNN chip for pixel-level snakes

Author

Brea, V.M. ; Vilarino, D.L. ; Cabello, D.

Author_Institution

Dept. of Electron. & Comput. Sci., Santiago de Compostela Univ., Spain

Volume

5

fYear

2004

fDate

23-26 May 2004

Abstract

This paper introduces the processing core of a full-custom mixed-signal CMOS chip intended for pixel-level snakes. Among the different parameters to optimize on the top-down design flow our methodology is focused on area. This approach results in a single-instruction-multiple-data chip implemented by a DTCNN with a correspondence between pixel and processing element. This is the first prototype for pixel-level snakes; an integrated circuit with a 9 × 9 resolution manufactured in a 0.25 μm CMOS STMicroelectronics technology process.

Keywords

CMOS integrated circuits; cellular neural nets; integrated circuit design; microprocessor chips; mixed analogue-digital integrated circuits; parallel processing; 0.25 micron; 9 × 9 resolution; CMOS process; STMicrolectronics; area optimization; integrated circuit; mixed-signal CMOS DTCNN chip; pixel element; pixel-level snakes; processing core; processing element; single-instruction-multiple-data chip; top-down design flow; CMOS process; CMOS technology; Cellular neural networks; Computer science; Data mining; Design methodology; Design optimization; Hardware; Monitoring; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1329679

Filename

1329679