DocumentCode
41869
Title
4×25 Gb/s Transceiver With Optical Front-end for 100 GbE System in 65 nm CMOS Technology
Author
Ping-Chuan Chiang ; Jhih-Yu Jiang ; Hao-Wei Hung ; Chin-Yang Wu ; Gaun-Sing Chen ; Jri Lee
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume
50
Issue
2
fYear
2015
fDate
Feb. 2015
Firstpage
573
Lastpage
585
Abstract
This paper presents a fully-integrated chipset for 4×25 Gb/s transceiver gearbox along with laser driver and photo detector front-ends. The transceiver provides 10:4 multiplexing and 4:10 demultiplexing conversion, with built-in clock generation, equalization, and amplification. The optical front-ends are realized as 4-element arrays, presenting remarkable performance with commercial vertical-cavity surface-emitting lasers and photodiodes. Feedforward equalizers and continuous-time linear equalizers are employed to compensate for loss and distortion in both electrical and optical domains. Fabricated in 65 nm CMOS technology, these chips can be lumped together as a compact module with performance exceeding typical 100 GbE standards.
Keywords
CMOS integrated circuits; continuous time systems; equalisers; multiplexing; transceivers; CMOS technology; built-in clock generation; continuous-time linear equalizers; feedforward equalizers; laser driver; optical front-end; photo detector front-ends; photodiodes; size 65 nm; transceiver gearbox; vertical-cavity surface-emitting lasers; Bandwidth; Boosting; CMOS integrated circuits; Clocks; Gain; Transceivers; Vertical cavity surface emitting lasers; 100 Gb/s Ethernet; clock and data recovery (CDR); demultiplexer; gearbox TRX; laser diode driver; limiting amplifier; multiplexer; transceiver; transimpedance amplifier (TIA);
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.2014.2365700
Filename
6955859
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