Partially reconfigurable matrix multiplication for area and time efficiency on FPGAs

This paper presents an architecture for matrix multiplication implemented on reconfigurable hardware with partially reconfigurable feature. The proposed design significantly reduces the size and achieves the minimum computation cycles for the n × n matrix multiplication. Compared with the linear array design (Jang et al., 2002) the area of our design is reduced by 72%-81% while the AT metrics (product of area and latency) is reduced by 40%-58% for matrix size between 3 × 3 and 48 × 48. The versatility of our design is demonstrated in different parameterisable instantiation to cater for different implementations with various time and area requirements. Partially reconfiguration allows us to reload the design contents with the minimum configuration overhead. The performance of our design is even better for larger matrices.