Multi-log processor - towards scalable event-driven multiprocessors

We present the multi-log processors, an event-driven multiprocessor. The functionality of the processor is defined by the triggering of events, maintained in a single event queue. The key feature of multi-log is that the entire register file and the event queue are shared. We describe the network architecture of the multi-log and discuss optimum layout schemes. This article describes two scalable event-driven multiprocessor architectures, the multi-log I and the multi-log II, and compares their VLSI complexities (gate delays, wire-length delays, and area). Both multiprocessors are implemented by a large collection of ALUs with controllers and on chip speculative L0 caches (together called logPs) connected together by a network of parallel-prefix tree circuits. A fat-tree network connects an interleaved memory to the logPs. These networks provide superscalar uniprocessor-like functionality, including register renaming, out-of-order event execution, and speculative event execution. Given 1 billion transistors on a single chip, the multi-log I architecture would have 256 logPs on chip, while the multi-log II architecture would allow for 1024 logPs on chip. We propose a new strategy to handle non-local events by introducing a mechanism to allow event transfers over the just described network, by means of event stealing. We also propose an instruction set architecture for the multi-log processor and give a programming model for event-driven applications. Scheduling events and stealing events are implemented in software. We suggest some innovative schemes for their implementation and analysis.