Title :
Topological BDP fault simulation method
Author :
Hahanov, Vladimir ; Hahanova, Irina ; Hyduke, Stanley
Author_Institution :
Kharkov Nat. Univ. of Radio Electron., Ukraine
fDate :
31 Aug.-3 Sept. 2004
Abstract :
The topological backtracking deductive-parallel fault simulation method (TBDP) is offered. It lies in backtracking of defects on topology of the circuit. It is oriented on gate-level description of the circuits. According to it the set of reconvergent fan-outs and tree-like structures is being defined on the description of the device.
Keywords :
backtracking; fault simulation; logic testing; tree data structures; backtracking deductive-parallel; circuit topology; defects backtracking; gate-level description; reconvergent fan-outs; topological BDP fault simulation; tree-like structures; Analytical models; Circuit faults; Circuit simulation; Circuit testing; Circuit topology; Digital systems; Electrical fault detection; Fault detection; System testing; Tree graphs;
Conference_Titel :
Digital System Design, 2004. DSD 2004. Euromicro Symposium on
Print_ISBN :
0-7695-2203-3
DOI :
10.1109/DSD.2004.1333308
