Implementation of multiple-valued flip-flips using pass transistor logic [flip-flips read flip-flops]

This paper presents the realization of multiple-valued flip-flops (MVFF) using pass transistor logic. Realization of MVFF has been discussed by many authors. The existing techniques are mainly extensions of binary flip-flops, based on CMOS or TTL logic. We propose here, two different design techniques for MVFF realized by pass transistors, which can be a promising alternative to static CMOS for deep sub-micron design. We have introduced a circuit consisting of multiple valued pass transistors which we call ´logical sum circuit´. This particular circuit is used as the elementary design component for our second approach in MVFF design. Our proposed MVFF circuits can be attractive for its inherent lesser power and component demands in comparison with existing techniques using MOS or TTL logic.