DocumentCode
420065
Title
Noise performance of 90 nm CMOS technology
Author
Becher, David ; Banerjee, Gargi ; Basco, Ricardo ; Hung, Celia ; Kuhn, Kelin ; Shih, Wei-kai
Author_Institution
Intel Corp., Hillsboro, OR, USA
Volume
1
fYear
2004
fDate
6-11 June 2004
Firstpage
17
Abstract
This work describes the noise figure performance of CMOS transistors at the 90 nm technology node. Noise parameters are measured from 2-18 GHz, resulting in a minimum noise figure less than 2 dB across the range of measured frequencies for both NMOS and PMOS. Data is presented showing the effect of total gate width, gate length, and bias on the noise parameters.
Keywords
CMOS integrated circuits; integrated circuit noise; integrated circuit testing; transistors; 2 to 18 GHz; 90 nm; CMOS technology; CMOS transistors; NMOS; PMOS; gate length; gate width; noise parameters; noise performance; Acoustic reflection; CMOS technology; Frequency measurement; Germanium silicon alloys; Heterojunction bipolar transistors; MOS devices; Noise figure; Noise measurement; Radio frequency; Silicon germanium;
fLanguage
English
Publisher
ieee
Conference_Titel
Microwave Symposium Digest, 2004 IEEE MTT-S International
ISSN
0149-645X
Print_ISBN
0-7803-8331-1
Type
conf
DOI
10.1109/MWSYM.2004.1335785
Filename
1335785
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