Measurements of Matching and Noise Performance of a Prototype Readout Chip in 40 nm CMOS Process for Hybrid Pixel Detectors

Author

Maj, P. ; Grybos, P. ; Szczygiel, R. ; Kmon, P. ; Kleczek, R. ; Drozd, A. ; Otfinowski, P. ; Deptuch, G.

Author_Institution

Dept. of Meas. & Electron., AGH Univ. of Sci. & Technol., Cracow, Poland

Volume

62

Issue

1

fYear

2015

fDate

Feb. 2015

Firstpage

359

Lastpage

367

Abstract

The paper presents a prototype integrated circuit built in a 40 nm CMOS process for readout of a hybrid pixel detector. The core of the IC constitutes a matrix of 18 ×24 pixels with the pixel size of 100 μm ×100 μm. The paper explains the functionality and the architecture of the IC, which is designed to operate in both the standard single photon counting mode and the single photon counting mode with interpixel communication to mitigate negative effects of charge sharing. This article focuses on the measurement results of the IC operating in the standard single photon counting mode. The measured ENC is 84e^- rms (for the peaking time of 48 ns), the gain is 79.7 μV/e^-, while the effective threshold dispersion is 21e^- rms.

Keywords

CMOS integrated circuits; X-ray detection; photon counting; readout electronics; CMOS process; effective threshold dispersion; hybrid pixel detectors; interpixel communication; prototype integrated circuit; prototype readout chip; standard single photon counting mode; Capacitance; Detectors; Integrated circuits; Noise; Photonics; Resistance; Transistors; Analog circuits; matching; noise; x-ray detectors;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2014.2385595

Filename

7027239