DocumentCode :
420497
Title :
Experimental evaluation of resonant clock distribution
Author :
Chueh, Juang-Ying ; Ziesler, Conrad H. ; Papaefthymiou, Marios C.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
fYear :
2004
fDate :
19-20 Feb. 2004
Firstpage :
135
Lastpage :
140
Abstract :
Energy recovery (a.k.a. adiabatic) systems present an attractive alternative to conventional designs due to their significant potential for reducing power. In practical versions of these systems, flip-flops are typically synchronized by a sinusoidal power-clock waveform through a resonant clock distribution network. Understanding clock skew is particularly important in energy recovery systems, because unlike their conventional counterparts, they do not use square clock waveforms or buffers. We have performed an experimental evaluation of clock skew in resonant H-shape clock distribution networks with sinusoidal waveforms. Our results show that compared to conventional clock distribution methodologies in high performance processors, properly designed low-power resonant clocking provides comparable or better skew. Our paper is the first study to suggest a number of practical design guidelines for low-skew resonant clocking, through a systematic investigation of the impact of width, spacing, and loading of the clock tree on clock skew.
Keywords :
buffer circuits; clocks; distribution networks; flip-flops; logic design; low-power electronics; resonant invertors; H-shape clock distribution networks; adiabatic systems; clock distribution methodologies; clock skew; clock tree; energy recovery systems; experimental evaluation; flip-flops; high performance processors; low-power resonant clocking; low-skew resonant clocking; power reduction; power-clock waveform; practical design guidelines; resonant clock distribution; sinusoidal waveforms; square clock waveforms; systematic investigation; Capacitance; Clocks; Flip-flops; Frequency; Power generation; RLC circuits; Resonance; Switches; Very large scale integration; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI, 2004. Proceedings. IEEE Computer society Annual Symposium on
Print_ISBN :
0-7695-2097-9
Type :
conf
DOI :
10.1109/ISVLSI.2004.1339520
Filename :
1339520
Link To Document :
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