DocumentCode :
421088
Title :
A surface potential model for predicting substrate noise coupling in integrated circuits
Author :
Kristiansson, Simon ; Ingvarson, Fredrik ; Kagganti, Shiva P. ; Jeppson, Kjell O.
Author_Institution :
Dept. of Microtechnology & Nanoscience, Chalmers Univ. of Technol., Goteborg, Sweden
fYear :
2004
fDate :
3-6 Oct. 2004
Firstpage :
497
Lastpage :
500
Abstract :
In integrated circuits, it must be verified that noise injected and transmitted through the substrate does not degrade the performance of sensitive circuitry present on the chip. In this paper, we present a simple analytic substrate model for evaluating substrate noise coupling. The model handles an arbitrary number of aggressor and victim devices as well as biased and floating chip backside. The model has been validated by measurements on test structures manufactured in a 0.35 μm CMOS process, and it is shown that the model gives an accurate description of the substrate noise coupling. For example, the noise suppressing properties of guard rings have been evaluated.
Keywords :
CMOS integrated circuits; coupled circuits; integrated circuit modelling; integrated circuit noise; interference suppression; surface potential; 0.35 micron; CMOS; IC substrate noise coupling; aggressor devices; biased chip backside; floating chip backside; guard rings noise suppressing properties; substrate injected noise; substrate transmitted noise; surface potential model; victim devices; Circuit testing; Coupling circuits; Degradation; Integrated circuit modeling; Integrated circuit noise; Manufacturing processes; Noise measurement; Predictive models; Semiconductor device measurement; Semiconductor device modeling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004
Print_ISBN :
0-7803-8495-4
Type :
conf
DOI :
10.1109/CICC.2004.1358866
Filename :
1358866
Link To Document :
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