Title :
Power estimation and thermal budgeting methodology for FPGAs
Author :
Lui, Henry Y. ; Lee, Chong H. ; Patel, Rakesh H.
Author_Institution :
Altera Corp., San Jose, CA, USA
Abstract :
The method used for power estimation and thermal budgeting on an FPGA product line, fabricated using 90 nm technology, is described in this paper. It addresses the reasons why state-of-the-art processes create power concerns on FPGAs, and describes methodologies that provide more relevant power and junction temperature estimations. Finally it suggests what can be done to improve the power budget and to balance the trade-offs between power and performance.
Keywords :
circuit simulation; field programmable gate arrays; integrated circuit design; integrated circuit modelling; leakage currents; logic simulation; 90 nm; FPGA; junction temperature estimation; leakage power estimation; power budget; power estimation; power/performance trade-offs; thermal budgeting; thermal runaway; Circuit simulation; Costs; Data mining; Field programmable gate arrays; Frequency; Semiconductor device packaging; State estimation; Technological innovation; Temperature; Thermal resistance;
Conference_Titel :
Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004
Print_ISBN :
0-7803-8495-4
DOI :
10.1109/CICC.2004.1358928
