A Systematic Approach to Design High-Order Phase-Locked Loops

A basic approach to improve the performance of phase-locked loop (PLL) under adverse grid condition is to incorporate a first-order low-pass filter (LPF) into its control loop. The first-order LPF, however, has a limited ability to suppress the grid disturbances. A natural thought to further improve the disturbance rejection capability of PLL is to use high-order LPFs. Application of high-order LPFs, however, results in high-order PLLs, which rather complicates the PLL analysis and design procedure. To overcome this challenge, a systematic method to design high-order PLLs is presented in this letter. The suggested approach has a general theme, which means it can be applied to design the PLL control parameters regardless of the order of in-loop LPF. The effectiveness of suggested design method is confirmed through different design cases.