RTL power estimation and optimization

Power consumption is a key limitation in many high-performance electronic systems today, ranging from mobile telecom to portable and desktop computers, especially when moving to nanometer technologies. Power is also a showstopper for many emerging applications like ambient intelligence and sensor networks, some of which are powered autonomously. Consequently, new design techniques and tools are needed to control and limit power consumption. This tutorial introduces innovative methodologies for successfully dealing with power estimation and optimization during the early stages of the design process. In particular, the presentation offers an insight of state-of-the-art techniques for power estimation at the RTL, describing how power consumption of components like data-path macros, glue and steering logic, memories, interconnect and clock wires can be efficiently modeled for fast and accurate power estimation. Then, the presentation shifts to power optimization, covering topics such as memory hierarchy and bus interface synthesis, advanced clock gating strategies and clock tree planning solutions. Most of the aforementioned approaches to RTL power estimation and optimization have now reached a significant level of maturity, and are thus finding their way into commercial CAD tools that are currently hitting the EDA market. Strengths and limitations of the design technology that is at the basis of such tools are discussed in detail throughout this tutorial.