DocumentCode :
4220
Title :
Controlled Degradation Stochastic Resonance in Adaptive Averaging Cell-Based Architectures
Author :
Aymerich, N. ; Cotofana, Sorin D. ; Rubio, Albert
Author_Institution :
Electron. Eng. Dept., Univ. Politec. de Catalunya, Barcelona, Spain
Volume :
12
Issue :
6
fYear :
2013
fDate :
Nov. 2013
Firstpage :
888
Lastpage :
896
Abstract :
In this paper, we first analyze the degradation stochastic resonance (DSR) effect in the context of adaptive averaging (AD-AVG) architectures. The AD-AVG is the adaptive version of the well-known AVG architecture . It is an optimized fault-tolerant design for future technologies with very high rates of failures and defects. With system degradation the AD-AVG reliability is diminishing, as expected, but at a certain moment in time it increases due to the DSR occurrence, which is counterintuitive. We study this phenomenon under various redundancy levels and noise condition. If we take for example a 20-input AD-AVG with particular noise conditions, our simulations indicate an initial yield decrease from 1 to 0.89 with the system degradation, then a grow up to 0.94 at the DSR peak, and finally a decrease to zero when the system is reaching its end of life. Subsequently, we introduce a method to induce DSR in an AD-AVG structure, regardless of the degradation level, when this results in reliability improvement. To achieve this, we augment the AD-AVG with per input controllable noise injectors that can be utilized to induce virtual circuit degradation and create the required conditions for the DSR peak appearance. With this scheme the beneficial DSR effect is created even though the actual DSR system degradation (aging conditions) is not reached. This allows us to provide an optimum and nearly flat reliability level at any time before the DSR peak degradation level. Our experiments suggest that when we apply this method to the same 20-input AD-AVG, we obtain a guaranteed yield level of 0.94 from fresh devices to the DSR peak degradation level with a maximum yield of 0.97. In this way, a minimum yield level can be guaranteed, by determining at design time the required AD-AVG redundancy that provides it, for the entire life of the system.
Keywords :
circuit optimisation; fault diagnosis; fault tolerance; nanoelectronics; redundancy; semiconductor device noise; semiconductor device reliability; stochastic processes; AD-AVG architectures; AD-AVG reliability; DSR effect; DSR occurrence; DSR peak degradation level; adaptive averaging cell-based architectures; aging conditions; controllable noise injectors; degradation stochastic resonance; failure defects; failure rate; noise conditions; optimized fault-tolerant design; redundancy levels; reliability improvement; system degradation; virtual circuit degradation; Aging; averaging cell; fault-tolerance; hardware redundancy; nanoscale technology; reliability;
fLanguage :
English
Journal_Title :
Nanotechnology, IEEE Transactions on
Publisher :
ieee
ISSN :
1536-125X
Type :
jour
DOI :
10.1109/TNANO.2013.2270301
Filename :
6544688
Link To Document :
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