Development of optimized SVPWM algorithm based on CPLD

Normal space vector PWM for three-phase voltage inverter has advantages in voltage utilization coefficient, current harmonic and over-modulation. Furthermore, the switching losses of the inverter are obviously reduced by controlling zero vectors properly. In this paper an optimized algorithm using neural network is presented, and the characteristics of neural network are introduced. This algorithm has advantages in increasing precision, reducing calculating time, reducing additional memory and the deterioration of the harmonic. This paper introduces a new CPLD (complex programmable logic device): ALTERA´S ACEX chip and EDA tool: MAX+PLUSII. For recent years, CPLD is increasingly developing very fast and has the advantages of high speed, large scale and easy-to-design software. It is convenient to use CPLD to design the circuit, simulate and verify the result, and it is also easy to debug the hardware using ISP (in system programmable). So this algorithm is easily realized. If it is necessary to adopt the improved algorithm, the only work we should do is to modify the algorithm in software, then download file to chip using ISP, it has nothing to do with the hardware circuit. Therefore, it is fit to design product and verify the algorithm using CPLD. At the end of this paper, the experimental results are shown, and the advantages are verified by these results.