Envelope-Tracking CMOS Power Amplifier Module for LTE Applications

An envelope-tracking (ET) CMOS power amplifier (PA) is fabricated using a 0.18- μm CMOS process. The module containing the supply modulator, the PA, and the output transformer is implemented on a printed circuit board (PCB). The CMOS PA employs the second and third harmonic controls at the input and the second harmonic short at the output for improved linearity. The impact on the nonlinearity of the cascode differential structure is studied and optimized. A proposed output transformer on the PCB minimizes the loss and enhances the efficiency of the PA. The ET on the gate of the common gate transistor is proposed to achieve high linearity and efficiency without using a digital pre-distortion technique. For a long-term evolution (LTE) signal at 1.85 GHz with a 10-MHz bandwidth and a 16QAM 7.5-dB peak-to-average power ratio, the ET CMOS PA module achieves a power-added efficiency of 34%, an error vector magnitude of 2.8%, and an adjacent channel leakage ratio of -34.2 dBc at an average output power of 26 dBm. The ET operation reduces the total current consumption by 10% to 34%, according to the power level, over that of the standalone PA for the LTE signal.