A new design strategy for the monolithic buck converters

A general approach is proposed for minimizing the chip area and minimizing the efficiency of the fully integrated CMOS continuous mode buck converters. It shows that most significant portion of the area is occupied by the passive component such as capacitors and inductors. Some design-oriented performance equations are proposed to show the key factors that determine the features of the converters in this paper. Chip size and conversion efficiency of buck converters are discussed to establish necessary guidelines for selecting parameters of converters. As an example, a monolithically integrated buck converter is designed based on a 0.5 mum CMOS technology. Simulation results indicate that the designed buck converter with minimized die size can deliver energy up to 450 mW at 3 V output under the condition of 5 V input. The converter efficiency is 76.8% at 80 MHz switching frequency