Title :
Fault-tolerant PLA-style circuit design for failure-prone nanometer CMOS and quantum device technologies
Author :
Schmid, Alexandre ; Leblebici, Yusuf
Author_Institution :
Swiss Fed. Inst. of Technol., Microelectron. Syst. Lab., Lausanne, Switzerland
Keywords :
CMOS digital integrated circuits; SPICE; fault tolerance; integrated circuit design; nanotechnology; programmable logic arrays; single electron transistors; PLA style matrix; SPICE simulations; circuit architecture; deep submicron CMOS circuits; error prone devices; failure prone nanometer CMOS device technology; fault immunity; fault tolerant PLA style circuit design; four layer architecture; functional robustness; high density digital systems; quantum device technology; redundancy factor; single electron transistor circuits; transistor level; CMOS technology; Circuit faults; Circuit synthesis; Computer architecture; Fault tolerance; Fault tolerant systems; Fluctuations; Microelectronics; Nanoscale devices; Robustness;
Conference_Titel :
Neural Networks, 2004. Proceedings. 2004 IEEE International Joint Conference on
Print_ISBN :
0-7803-8359-1
DOI :
10.1109/IJCNN.2004.1380914
