Title :
A charge recycling differential noise immune perceptron
Author :
Nyathi, Jabulani ; Beiu, Valeriu ; Tatapudi, Suryanarayana ; Betowski, David J.
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA
Keywords :
CMOS logic circuits; integrated circuit noise; logic gates; perceptrons; threshold logic; 0.25 micron; 2.5 V; CMOS technology; charge recycling; differential neural inspired gate; differential noise immune perceptron; noise suppression logic blocks; split level precharge differential logic; threshold logic bank; threshold logic gates; Boolean functions; CMOS logic circuits; CMOS technology; Logic design; Logic devices; Logic gates; Neurons; Recycling; Sensor arrays; Switches;
Conference_Titel :
Neural Networks, 2004. Proceedings. 2004 IEEE International Joint Conference on
Print_ISBN :
0-7803-8359-1
DOI :
10.1109/IJCNN.2004.1380921
