Title :
Experimental Measurement of A Novel Power Gating Structure with Intermediate Power Saving Mode
Author :
Suhwan Kim ; Kosonocky, S.V. ; Knebel, D.R. ; Stawiasz, Kevin
Author_Institution :
Seoul National Univestiy, Korea
Abstract :
A novel power gating structure is proposed for low-power, high-performance VLSI. This power gating structure supports an intermediate power saving mode as well as a traditional power cut-off mode. To evaluate our power gating structure, we design and fabricate three different macros in 0.13 µm CMOS bulk technology. Our measurement results show that the additional intermediate power-mode allows us to cover various power-performance trade-off regimes, compared to conventional power gating structures.
Keywords :
clock gating; ground bounce; inductive noise; power gating; system-on-a-chip (SOC) design; wake-up latency; clock gating; ground bounce; inductive noise; power gating; system-on-a-chip (SOC) design; wake-up latency;
Conference_Titel :
Low Power Electronics and Design, 2004. ISLPED '04. Proceedings of the 2004 International Symposium on
Conference_Location :
Newport Beach, CA, USA
Print_ISBN :
1-58113-929-2
