DocumentCode :
424451
Title :
An Efficient Voltage Scaling Algorithm for Complex SoCs with Few Number of Voltage Modes
Author :
Gorjiara, B. ; Bagherzadeh, Nader ; Chou, Po-Cheng
Author_Institution :
University of California, Irvine
fYear :
2004
fDate :
11-11 Aug. 2004
Firstpage :
381
Lastpage :
386
Abstract :
Increasing demand for larger high-performance applications requires developing more complex systems with hundreds of processing cores on a single chip. To allow dynamic voltage scaling in each on-chip cores individually, many on-chip voltage regulators must be used. However, the limitations in implementation of on-chip inductors can reduce the efficiency, accuracy and the number of voltage modes generated by regulators. Therefore the future voltage scheduling algorithms must be efficient, even in the presence of few voltage modes; and fast, in order to handle complex applications. Techniques proposed to date, need many fine-grained voltage modes to produce energy efficient results and their quality degrades significantly as the number of modes decreases. This paper presents a new technique called Adaptive Stochastic Gradient Voltage and Task Scheduling (ASG-VTS) that quickly generates very energy efficient results irrespective of the number of available voltage modes. The results of comparing our algorithm to the most efficient approaches (RVS and EE-GLSA) show that in the presence of only four valid modes, the ASG-VTS saves up to 26% and 33% more energy. On the other hand, other approaches require at least ten modes to reach the same level of energy saving that ASG-VTS achieves with only four modes. Therefore our algorithm can also be used to explore and minimize the number of required voltage levels in the system.
Keywords :
Dynamic Voltage Scaling (DVS); and multi-processor systems; heterogeneous systems; optimization; power management; scheduling; stochastic gradient search; Dynamic Voltage Scaling (DVS); and multi-processor systems; heterogeneous systems; optimization; power management; scheduling; stochastic gradient search;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Low Power Electronics and Design, 2004. ISLPED '04. Proceedings of the 2004 International Symposium on
Conference_Location :
Newport Beach, CA, USA
Print_ISBN :
1-58113-929-2
Type :
conf
Filename :
1383023
Link To Document :
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