A quasi-delay-insensitive method to overcome transistor variation

Synchronous design methods have intrinsic performance overheads due to their use of the global clock and timing assumptions. In future manufacturing processes not only may it become impractical to distribute the clock globally but any timing assumptions will require increasingly large timing margins. This paper presents a method of overcoming these overheads to take full advantage of the improved manufacturing processes. By removing the clock and using self-timed techniques clock related constraints can be discarded. Removing its timing assumptions allows a circuit to perform at a higher speed. An asynchronous logic method allowing the generation of results before the presentation of all input and techniques to allow speculatively fetched data to be removed with a reduced impact on the performance are presented.