Title :
Post-packaging auto repair techniques for fast row cycle embedded DRAM
Author :
Wada, Osamu ; Namekawa, Toshimasa ; Ito, Hioshi ; Nakayama, Atsushi ; Fujii, Shuso
Author_Institution :
Semicond. Co., Toshiba Corp., Kawasaki, Japan
Abstract :
A test flow using a auto repair technique has also been proposed. It assumes a conventional wafer testing, but puts much weight on the post-package test by utilizing the proposed auto repair technique. This is implemented in a 36 Mb embedded DRAM macro of 6ns cycle time. It consists of internal compare circuit, redundancy analyzer, and anti-fuses. The internal auto programming of anti-fuse fixes post-packaging failures that might appear by final at-speed test and contributes to yield improvement.
Keywords :
DRAM chips; integrated circuit testing; logic testing; 6 ns; anti-fuses; at-speed test; conventional wafer testing; fast row cycle embedded DRAM; internal auto programming; internal compare circuit; post-package test; post-packaging auto repair technique; post-packaging failures; redundancy analyzer; Built-in self-test; Circuits; Failure analysis; Frequency; Fuses; Packaging; Random access memory; Testing; Thermal stresses; Wafer scale integration;
Conference_Titel :
Test Conference, 2004. Proceedings. ITC 2004. International
Print_ISBN :
0-7803-8580-2
DOI :
10.1109/TEST.2004.1387367
