Affordable and effective screening of delay defects in ASICs using the inline resistance fault model

Transition delay fault (TDF) testing has become a necessary test method in very deep sub micron (VDSM) technologies due to the presence of resistive defects that cause subtle timing failures. The transition delay fault model is based on a slow-to-rise and slow-to-fall fault at each node in the circuit. Some resistive defects such as resistive vias actually induce both faults and the TDF test set can contain unnecessary test patterns for proper screening of this type of defect. The inline resistance fault (IRF) model more accurately represents this defect type and is studied in depth in This work. ATPG experimental results show that IRF patterns can be generated 1.4 to 1.8 times faster with 45% to 58% fewer patterns than traditional TDF patterns. IRF and TDF pattern test results are presented and show that the more expensive TDF remains a more comprehensive test than IRF as expected, but that the quality impact of using only the IRF test set is minimal, especially when combined with effective IDDQ outlier screening such as statistical post processing. Additionally, a methodology is presented for the determination of the number of delay defects that behave according to each model from the test data alone, which is necessary to accurately determine delay defect coverage from multiple test coverage metrics.