A configurable direct-conversion/superheterodyne W-CDMA baseband down-link channel

A configurable baseband downlink (BDL) channel of a W-CDMA analog codec suitable to be used with both direct conversion (DIR) and superheterodyne (SHT) architectures is presented. The BDL is an analog signal processor consisting of on-chip calibrated programmable active-RC filters and oversampled 6-bit analog-to-digital (A/D) pipeline converters, which sufficiently suppress the adjacent channel and other interferers before digital signal processing on an external DSP. A digital-to-analog converter based DC-offset cancellation system allows us to reduce the channel offset down to 0.25 LSB of the BDL channel resolution. The system has been successfully integrated in a double-poly 0.6 μm CMOS process. Experimental results show that the designed BDL channel achieves 38.4 dB SNDR, 43 dB SFDR in DIR mode and 38.3 dB SNDR, 42.8 dB SFDR in SHT mode with an overall power consumption of 49 mW (in DIR mode) and 58 mW (in SHT mode) from a single 2.8 V power supply. A low-power consumption mode, which operates on the A/D converters, allows us to further reduce these values down to 41 mW/50 mW (respectively in DIR and SHT mode) without significant detrimental effects to the overall BDL linearity performance.