Stochastic Modeling of Positive Bias Temperature Instability in High- Metal Gate nMOSFETs

Positive bias temperature instability (PBTI) has become one of the major reliability concerns in the present day CMOS technology. The PBTI mostly degrades the performance of high-κ/metal gate (HK/MG) nMOSFETs and is dominated by time dependent stress induced trap generation. The PBTI models proposed so far in different literature are deterministic in nature and overlook the randomness of the temporal degradation of transistor threshold voltage, V_th. In this paper, we present a stochastic model for PBTI to predict the behavior of HK/MG nMOSFETs under inversion mode stress. The model is scalable and is verified against experimental data from two different groups. Our model separately considers each trap to predict their impact on device performance. The simulations are carried out at accelerated voltage and temperature conditions and we noted the variations in V_th. In addition, we have analyzed the impact of PBTI on the performance of a ring oscillator and concluded that the circuit speed suffers significant degradation due to this effect. We have also observed that the adverse effect of PBTI becomes more severe as we go deeper into the nanometer technology.