A gate-level model for morphogenetic evolvable hardware

Traditional approaches to evolvable hardware (EHW), in which the FPGA configuration is directly encoded, have not scaled well with increasing problem complexity. To overcome this there have been moves towards encoding a growth process, however, these have tended to abstract away the underlying FPGA architecture, limiting evolution´s ability to find novel solutions free of designer bias. In This work we present a morphogenetic EHW model where growth is directed largely by the gate-level state of the FPGA. Initial results are presented that show that our approach outperforms a traditional EHW approach using a direct encoding, and importantly, is able to scale to larger, more complex, problems with only a modest increase in the number of generations required to find an optimal solution.