Title :
A high-performance architecture of arithmetic coder in JPEG2000
Author :
Pastuszak, Grzegorz
Author_Institution :
Inst. of Radioelectron., Warsaw Univ. of Technol.
Abstract :
This paper presents a high-performance architecture of the arithmetic coder for the embedded block coding algorithm in JPEG2000. The dedicated pipeline architecture, enhanced by the inverse multiple branch selection (IMBS) method, is proposed to code two context-symbol pairs per clock cycle. The overall design was implemented in VHDL and synthesized for FPGA devices. Simulation results show that it can process about 17 million samples at 77 MHz working frequency
Keywords :
arithmetic codes; field programmable gate arrays; hardware description languages; image coding; pipeline processing; 77 MHz; FPGA; IMBS method; JPEG2000; VHDL; arithmetic coder; context-symbol pair coding; embedded block coding algorithm; inverse multiple branch selection method; pipeline architecture; Arithmetic; Block codes; Clocks; Field programmable gate arrays; Image coding; Pipelines; Switches; Throughput; Timing; Transform coding;
Conference_Titel :
Multimedia and Expo, 2004. ICME '04. 2004 IEEE International Conference on
Conference_Location :
Taipei
Print_ISBN :
0-7803-8603-5
DOI :
10.1109/ICME.2004.1394503
