DocumentCode :
427429
Title :
Chip-package co-design of power distribution network for system-in-package applications
Author :
Kim, Gawon ; Kam, Dong Gun ; Chung, Daehyun ; Kim, Joungho
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., KAIST, Daejeon, South Korea
fYear :
2004
fDate :
8-10 Dec. 2004
Firstpage :
499
Lastpage :
501
Abstract :
A new figure of merit for chip-package co-design of a power distribution network (PDN) is needed, not merely a voltage difference between power and ground at each hierarchy. In order to measure power supply noise as it is actually seen by the circuits in various locations on a chip, we need to chase the power/ground voltage with reference to a system ground. A PDN has two current paths; a series path and a shunt path. While the shunt path determines the voltage difference, the series path controls the power/ground voltage itself. Therefore, a balanced approach is strongly required rather than an excessive attention to the shunt path.
Keywords :
chip scale packaging; integrated circuit design; multichip modules; chip-package codesign; current path; ground voltage; power distribution network; power supply noise measurement; power voltage; series path; shunt path; system-in-package; voltage difference; Capacitors; Design methodology; Fluctuations; Frequency domain analysis; Impedance; Noise measurement; Packaging; Power measurement; Power systems; Voltage control;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Packaging Technology Conference, 2004. EPTC 2004. Proceedings of 6th
Print_ISBN :
0-7803-8821-6
Type :
conf
DOI :
10.1109/EPTC.2004.1396659
Filename :
1396659
Link To Document :
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